The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set ...

SILICON VALLEY, Calif.--(BUSINESS WIRE)--Ashling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling’s ...

Western Digital has announced that it's completed work on its Swerv RISC-V CPU core and has published the register-transfer level (RTL) abstraction of the design. Publishing the RTL code allows other ...

Processor vendors have always tried to create a large software ecosystem around their products, because it creates stickiness and it naturally “locks-in” large numbers of customers who have invested ...

Forward-looking: Despite some setbacks and general uncertainty about the future, the RISC-V instruction set architecture (ISA) is slowly growing its presence in the open-source market. Now, there's a ...

In almost every discussion about RISC-V's position in the ecosystem, the instruction set architecture (ISA) is often seen as a direct competitor to Arm. Most people view the two ISAs as being engaged ...

Many companies today are exploring free, open-source hardware and software as an alternative to closed, costly instruction set architectures (ISAs). RISC-V is a free, open, and extensible ISA that’s ...

Alibaba has just made a laptop called the Alibaba Roma RISC-V laptop that gets its processor based on the RISC-V ISA, which is open-sourced. This is interesting because the RISC-V processors are more ...

The world’s first laptop to use the RISC-V open source instruction set architecture (ISA) will reportedly start shipping in September. The Roma laptop is available for preorder on Xcalibyte’s website, ...