IEEE

Advanced 2T0C DRAM Technologies for Processing-in-Memory—Part I: Vertical Transistor on Gate (VTG) DRAM Cell Structure

Abstract: Two-transistor-zero-capacitor (2T0C) DRAM cell has been proposed and extensively investigated as a memory device for processing-in-memory (PIM) applications. In this two-part article, we ...
C&EN

Polarized Tunneling Transistor for Ultrafast Memory

School of Integrated Circuits & Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, China Institute of Marine Science and Technology, ...
IEEE

FerroHEMTs: High-Current and High-Speed All-Epitaxial AlScN/GaN Ferroelectric Transistors

Abstract: We report the first observation of ferroelectric gating in AlScN barrier wide-bandgap nitride transistors. These FerroHEMT devices realized by direct epitaxial growth represent a new class ...
C&EN

Sources and Mechanism of Degradation in p-Type Thiophene-Based Organic Electrochemical Transistors

Dept. of Biomedical Engineering, Northwestern University, Evanston, Illinois 60208, United States Simpson Querrey Institute, Northwestern University, Chicago ...